High speed ADC

• المؤلف الرئيسي: Lin, Esmond Chengyuan
• مؤلفون آخرون: Chang, Joseph Sylvester
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2017
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/71830

This report presents a simulation model design of a 10-bits pipelined ADC with background calibration. The proposed architecture includes a 3-bit ADC, five 1.5-bits ADC and a 2-bit ADC in a cascade. Some non-ideal errors and offsets are introduced in the pipelined ADC during simulation to model the...