Automated DFT verification and pattern generation methodology for mixed signal SoC

• Main Author: Bellam Venkata Sai Kiran
• Other Authors: Gwee Bah Hwee
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73118
• Institution: Nanyang Technological University

Design for Test (DFT) is a complex and critical activity in modern SoC design cycle. A typical SoC has multiple IPs with different test requirements. The verification of these test schemes is usually addressed ad-hoc in a project which leads to missing test cases and delay in project schedules. Moreover, the need to support the test teams by providing patterns required for silicon tests puts additional requirements on the verification process. Test cases developed to simulate functional tests should be cyclised and converted to patternsrequiring cumbersome pattern conversion flow. Test patterns generated from EDA tool for structural tests should be simulated and verified to match simulated data with tester data. This dissertation aims to develop a comprehensive verification environment using Universal Verification Methodology (UVM) to support all verification activities involved in DFT for mixed signal SoC. The concept of transaction level modelling (TLM) has been exploited to record the transactions and automatically generate test patterns from the simulation of test cases thus avoiding additional pattern conversion flow. A Verilog Procedural Interface (VPI) based approach has been developed and integrated into this environment to directly run simulations from test patterns reducing the debug time involved. A configurable and reusable verification environment with UVM classes populated with methods to verify widely used test schemes has been developed to achieve over 99% code coverage for test logic. Single simulation snapshot sharing scheme has been developed for all simulations to reduce the overall simulation time by 25%. This methodology provides a means to directly read test pattern formats like Standard Test Interface Language (STIL) and Serial Vector Format (SVF) in a simulation environment avoiding the need for pattern conversion software. A general purpose pattern writing flow which can be configured for writing out patterns in above formats directly from the simulation environment has been developed and successfully ported to ATE environment for running silicon production tests.