3D interconnect-based segmented bus architecture modelling and exploration
The communication and memory organization in system on chip are a major source of energy consumption. Future sub-10 nano-scale process and interconnect technologies will lead to higher performances but also to an increased energy bottleneck. To obtain high bandwidth, several solutions have been expl...
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| Format: | Theses and Dissertations |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/73127 |
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| Institution: | Nanyang Technological University |
| Language: | English |