3D interconnect-based segmented bus architecture modelling and exploration

• Main Author: Singh, Gagandeep
• Other Authors: Andreas Herkersdorf
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73127
• Institution: Nanyang Technological University

The communication and memory organization in system on chip are a major source of energy consumption. Future sub-10 nano-scale process and interconnect technologies will lead to higher performances but also to an increased energy bottleneck. To obtain high bandwidth, several solutions have been expl...