Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP
In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented...
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2018
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| Online Access: | http://hdl.handle.net/10356/73139 |
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sg-ntu-dr.10356-731392023-07-04T15:05:43Z Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP Yang, Shi Lim Meng Hiot School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented during the project period. The simulation environment is mainly used for preliminary and functional checks, and the emulation environment is chosen for further verification due to its much higher run speed compared to simulation. Master of Science (Integrated Circuit Design) 2018-01-03T07:34:57Z 2018-01-03T07:34:57Z 2018 Thesis http://hdl.handle.net/10356/73139 en 68 p. application/pdf |
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Nanyang Technological University |
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Asia |
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Singapore Singapore |
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English |
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DRNTU::Engineering::Electrical and electronic engineering |
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DRNTU::Engineering::Electrical and electronic engineering Yang, Shi Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| description |
In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented during the project period. The simulation environment is mainly used for preliminary and functional checks, and the emulation environment is chosen for further verification due to its much higher run speed compared to simulation. |
| author2 |
Lim Meng Hiot |
| author_facet |
Lim Meng Hiot Yang, Shi |
| format |
Theses and Dissertations |
| author |
Yang, Shi |
| author_sort |
Yang, Shi |
| title |
Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| title_short |
Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| title_full |
Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| title_fullStr |
Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| title_full_unstemmed |
Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP |
| title_sort |
design and implementation of a synthesizable test-bench for testing the ldpc decoder ip |
| publishDate |
2018 |
| url |
http://hdl.handle.net/10356/73139 |
| _version_ |
1772829116014264320 |