Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP

• Main Author: Yang, Shi
• Other Authors: Lim Meng Hiot
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73139
• Institution: Nanyang Technological University

In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented...