Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails....
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| Format: | Theses and Dissertations |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/73145 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails. A correlation study has been targeted under this project where a DDR controller module with sizable logic and memory elements will be subjected to scan patterns. Simulation dump of these pattern will be analysed on power analysis tool and the result will be matched with information provided by standard cell library and scan tool. Final report will utilized as a reference when planning test of an actual SOC design including test-partitioning and to the possibility of concurrent testing. |
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