Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design

Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails....

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Main Author:	Wang, Yunlong
Other Authors:	Lim Meng Hiot
Format:	Theses and Dissertations
Language:	English
Published:	2018
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	http://hdl.handle.net/10356/73145
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-73145
record_format	dspace
spelling	sg-ntu-dr.10356-731452023-07-04T15:05:31Z Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design Wang, Yunlong Lim Meng Hiot School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails. A correlation study has been targeted under this project where a DDR controller module with sizable logic and memory elements will be subjected to scan patterns. Simulation dump of these pattern will be analysed on power analysis tool and the result will be matched with information provided by standard cell library and scan tool. Final report will utilized as a reference when planning test of an actual SOC design including test-partitioning and to the possibility of concurrent testing. Master of Science (Integrated Circuit Design) 2018-01-03T07:46:56Z 2018-01-03T07:46:56Z 2018 Thesis http://hdl.handle.net/10356/73145 en 74 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Wang, Yunlong Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
description	Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails. A correlation study has been targeted under this project where a DDR controller module with sizable logic and memory elements will be subjected to scan patterns. Simulation dump of these pattern will be analysed on power analysis tool and the result will be matched with information provided by standard cell library and scan tool. Final report will utilized as a reference when planning test of an actual SOC design including test-partitioning and to the possibility of concurrent testing.
author2	Lim Meng Hiot
author_facet	Lim Meng Hiot Wang, Yunlong
format	Theses and Dissertations
author	Wang, Yunlong
author_sort	Wang, Yunlong
title	Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
title_short	Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
title_full	Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
title_fullStr	Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
title_full_unstemmed	Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
title_sort	correlation analysis of power consumption by atpg test with library data of a ddr memory controller design
publishDate	2018
url	http://hdl.handle.net/10356/73145
_version_	1772828621430325248

Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design

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