Correlation analysis of power consumption by ATPG test with library data of a DDR memory controller design
Toggle rate of the logic and memories during test is much higher than in function application. High toggle rate is desired to achieve test coverage faster and hence to have shorter test time. The flip side is that power consumption during test become higher, leading to IR drop and hence false fails....
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2018
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| 在線閱讀: | http://hdl.handle.net/10356/73145 |
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| 機構: | Nanyang Technological University |
| 語言: | English |