Development of micro-strip GaN-on-SiC backside via holes process
GaN-on-SiC HEMTs have gained remarkable attention due to their potential to revolutionize power and RF electronics as it has highest output power density amongst all solid state semiconductor devices Although much progress in HEMTs has been made, via-holes remain critical routes to improve DC and RF...
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sg-ntu-dr.10356-746972023-07-07T16:32:41Z Development of micro-strip GaN-on-SiC backside via holes process Yu, Zhuoran Wang Hong School of Electrical and Electronic Engineering Temasek Laboratories @ NTU DRNTU::Engineering GaN-on-SiC HEMTs have gained remarkable attention due to their potential to revolutionize power and RF electronics as it has highest output power density amongst all solid state semiconductor devices Although much progress in HEMTs has been made, via-holes remain critical routes to improve DC and RF electrical performance for micro-strip circuits. From this project, you can understand how the Via hole was fabricated in the cleanroom by a lot of experiments like Lapping, Dry etching, photolithograph, Ni Plating and so on. My project will mainly concentrate on the processes of SiC lapping and dry etching. The details will be introduced in the following chapters. Bachelor of Engineering 2018-05-23T03:38:02Z 2018-05-23T03:38:02Z 2018 Final Year Project (FYP) http://hdl.handle.net/10356/74697 en Nanyang Technological University 50 p. application/pdf |
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DRNTU::Engineering Yu, Zhuoran Development of micro-strip GaN-on-SiC backside via holes process |
| description |
GaN-on-SiC HEMTs have gained remarkable attention due to their potential to revolutionize power and RF electronics as it has highest output power density amongst all solid state semiconductor devices Although much progress in HEMTs has been made, via-holes remain critical routes to improve DC and RF electrical performance for micro-strip circuits. From this project, you can understand how the Via hole was fabricated in the cleanroom by a lot of experiments like Lapping, Dry etching, photolithograph, Ni Plating and so on. My project will mainly concentrate on the processes of SiC lapping and dry etching. The details will be introduced in the following chapters. |
| author2 |
Wang Hong |
| author_facet |
Wang Hong Yu, Zhuoran |
| format |
Final Year Project |
| author |
Yu, Zhuoran |
| author_sort |
Yu, Zhuoran |
| title |
Development of micro-strip GaN-on-SiC backside via holes process |
| title_short |
Development of micro-strip GaN-on-SiC backside via holes process |
| title_full |
Development of micro-strip GaN-on-SiC backside via holes process |
| title_fullStr |
Development of micro-strip GaN-on-SiC backside via holes process |
| title_full_unstemmed |
Development of micro-strip GaN-on-SiC backside via holes process |
| title_sort |
development of micro-strip gan-on-sic backside via holes process |
| publishDate |
2018 |
| url |
http://hdl.handle.net/10356/74697 |
| _version_ |
1772825256601321472 |