Analysis of memory BIST architecture flow

• Main Author: Sharma, Anmol
• Other Authors: Chang Chip Hong
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76070
• Institution: Nanyang Technological University

The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in memory testing. Memory Built-in self-test (BIST) is the most widely used solution for memory testing. MBIST is defined as a method used for insertion of embedded memory controllers inside the chip to make its memories fully testable after manufacturing. This work focusses on implementation of different memory BIST architecture optimization techniques to generate MBIST architectures for given design specifications. These architectures are then compared on the basis of power consumption per memory controller, total cell area and test time required per memory controller. The analysis of these architectures is done to recommend the most optimized MBIST architecture for a given design specification. This work also provides a comprehensive study of two memory built-in self-test flows which are predominantly used in IC design industry to generate MBIST architecture. The two flows used for this purpose are Tessent Memory BIST LV Flow and Tessent Memory BIST Shell Flow.