Power management for image sensor
The pixels in CMOS Image Sensor (CIS) require clean reference voltages for the gate or drain bias of pixel MOS transistors to ensure good image quality. The generation of such pixel supply voltages, as part of the CIS Power Management design, is typically realized by a series of linear regulators. T...
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| Format: | Theses and Dissertations |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/76081 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The pixels in CMOS Image Sensor (CIS) require clean reference voltages for the gate or drain bias of pixel MOS transistors to ensure good image quality. The generation of such pixel supply voltages, as part of the CIS Power Management design, is typically realized by a series of linear regulators. This thesis aims to talk about the existing pixel regulator design and to identify potential area for improvements, such as PSRR, stability etc. In addition, my work on bandgap and system simulation is also contained in this thesis, which support the pixel to have good performance. |
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