Ultra-low voltage SRAM design

• Main Author: Wong, Timothy Ting Hin
• Other Authors: Kim Tae Hyoung
• Format: Final Year Project
• Language: English
• Published: 2019
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/77830
• Institution: Nanyang Technological University

The requirement for smaller, lighter yet increasingly powerful electronic devices has never been greater. Miniaturisation of semiconductor technology is pushing Moore’s Law to its limit, and transistor densities are higher than ever before. Power consumption is hence becoming a significant issue, especially noticeable in integrated circuits such as Static Random-Access memory (SRAM) which can occupy over 60% of die area. Hence, the present study uses Cadence Virtuoso ADE to analyse commonly utilised 4T, 6T and 8T SRAM bit-cell topologies, and quantifies the effect of voltage scaling to sub-threshold levels, process variation and temperature variance on the static noise margins (SNMs), leakage currents and read/write energies. Furthermore, a 4-kb 256 × 16 SRAM module is implemented with 6T cells and shown to operate at 400 mV. It is found that Ultra-Low Voltage (ULV) operation of SRAM can offer over 90% decrease in active power consumption, and upwards of 95% reduction in leakage with a reduction from 1.5 V to 400 mV – albeit at a trade-off with stability margins. Operation at higher temperatures have also demonstrated up to 85% increase of leakage power for an increase of 80 C from ambient.