Analog equalizers and SerDes receiver analog front end for 32 Gb/s wireline communication

• Main Author: Balachandran, Arya
• Other Authors: Boon Chirn Chye
• Format: Theses and Dissertations
• Language: English
• Published: 2019
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/78832
• Institution: Nanyang Technological University

Options for area-efficient and power-efficient equalization with maximum timing integrity become increasingly crucial for wireline receivers entering data rate more than 10 Gb/s. Different techniques for equalization at the receiver end have already been proposed in the past. Many of these solutions, though are highly suitable for data rate > 25 Gb/s, are not power- and area-efficient to be used in compact wireline system-on-chip (SoC) owing to the use of bulky inductors which are necessary to meet the desired bandwidth. The widely used equalizers also tend to ignore the low frequency loss in the channel, while addressing the traditional high frequency loss in the channel. However, over long measurement intervals, the low frequency loss manifests as increased datadependent jitter (DDJ) and worsens the timing integrity of the equalized signal. In this thesis, three different power-efficient inductorless analog equalizer designs that improve the timing integrity of the equalized signal are proposed. The first design which operates at 13 Gb/s proposes an inductorless analog equalizer design with low, intermediate and high frequency equalization. The equalizer design uses conventional linear equalizer architecture together with active feedback topology which extends the bandwidth for the inductorless design. The proposed linear equalizer improves the jitter of a conventional CTLE from 0.41 unit interval (UI) to 0.12 UI for a 231-1 input PRBS in the presence of channel loss of 15 dB, with a power efficiency of 1.07 mW/Gb/s. The first equalizer design implements dedicated circuit logic for low frequency equalization and hence does not offer a power-efficient solution at data rate higher than 25 Gb/s. To address this challenge, a second equalizer design is proposed. The proposed equalizer design targets an inductorless and powerefficient solution for a data rate of 32 Gb/s. The proposed analog equalizer utilizes a triple-gate control which entails that a low frequency equalization is simultaneously achieved at minimum area overhead. At a peaking of 21 dB at Nyquist, the proposed design measures a peak-to-peak jitter of 0.17 UI at the equalizer output for a 231-1 PRBS input pattern. Under a 1.2 V supply, the power efficiency is measured as 0.53 mW/Gb/s. The adaptation logic of the tuning controls in the second equalizer, especially for the low frequency loss poses technical challenges in channel-aware designs. This conduces that a linear equalizer as proposed in the second design be combined with a nonlinear equalizer for better flexibility to adapt the equalizer to minimize the timing jitter. This is especially significant when the transmitted clock has to be recovered to retime the received data. Thus, the third design proposes an inductorless 32 Gb/s wireline receiver analog front end (AFE) with a linear equalizer and a novel half-rate distributed decision feedback equalizing (DFE) scheme. The proposed distributed DFE scheme addresses the problem of edge ISI, thus ensuring better timing jitter at the clock edges. This in turn helps in accurate sampling of the data edges while maintaining the vertical height at the centre of the sampled data. Measurement results show that the proposed design has a power efficiency of 3.53 mW/Gb/s at 1.2 V and exhibits a Bit Error Rate (BER) < 10-12 at a data rate of 32 Gb/s.