Analog equalizers and SerDes receiver analog front end for 32 Gb/s wireline communication

Options for area-efficient and power-efficient equalization with maximum timing integrity become increasingly crucial for wireline receivers entering data rate more than 10 Gb/s. Different techniques for equalization at the receiver end have already been proposed in the past. Many of these soluti...

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Bibliographic Details
Main Author: Balachandran, Arya
Other Authors: Boon Chirn Chye
Format: Theses and Dissertations
Language:English
Published: 2019
Subjects:
Online Access:http://hdl.handle.net/10356/78832
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Institution: Nanyang Technological University
Language: English

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