Modeling and layout optimization of differential inductors for Silicon-based RFIC applications

• المؤلفون الرئيسيون: Sia, Choon Beng, Ong, Beng Hwee, Lim, Wei Meng, Yeo, Kiat Seng, Alam, Tariq
• مؤلفون آخرون: School of Electrical and Electronic Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2009
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/79961; http://hdl.handle.net/10220/4710

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.