Modeling and layout optimization of differential inductors for Silicon-based RFIC applications

Modeling and layout optimization of differential inductors for Silicon-based RFIC applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs...

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Main Authors: Sia, Choon Beng, Ong, Beng Hwee, Lim, Wei Meng, Yeo, Kiat Seng, Alam, Tariq
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2009
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:https://hdl.handle.net/10356/79961
http://hdl.handle.net/10220/4710
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-799612020-03-07T13:57:22Z Modeling and layout optimization of differential inductors for Silicon-based RFIC applications Sia, Choon Beng Ong, Beng Hwee Lim, Wei Meng Yeo, Kiat Seng Alam, Tariq School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance. Published version 2009-07-28T04:17:45Z 2019-12-06T13:37:38Z 2009-07-28T04:17:45Z 2019-12-06T13:37:38Z 2008 2008 Journal Article Sia, C. B., Ong, B. H., Lim, W. M., Yeo, K. S., & Alam, T. (2008). Modeling and layout optimization of differential inductors for Silicon-based RFIC applications. IEEE Transactions on Electron Devices, 55(4), 1058-1066. 0018-9383 https://hdl.handle.net/10356/79961 http://hdl.handle.net/10220/4710 10.1109/TED.2008.917536 en IEEE transactions on electron devices © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 9 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Sia, Choon Beng
Ong, Beng Hwee
Lim, Wei Meng
Yeo, Kiat Seng
Alam, Tariq
Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
description A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Sia, Choon Beng
Ong, Beng Hwee
Lim, Wei Meng
Yeo, Kiat Seng
Alam, Tariq
format Article
author Sia, Choon Beng
Ong, Beng Hwee
Lim, Wei Meng
Yeo, Kiat Seng
Alam, Tariq
author_sort Sia, Choon Beng
title Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
title_short Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
title_full Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
title_fullStr Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
title_full_unstemmed Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
title_sort modeling and layout optimization of differential inductors for silicon-based rfic applications
publishDate 2009
url https://hdl.handle.net/10356/79961
http://hdl.handle.net/10220/4710
_version_ 1681035834707410944

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