A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks
Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these app...
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| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2016
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/80907 http://hdl.handle.net/10220/41169 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these approaches require high voltages (≈3-12V) for weight update and entail high energy for learning (≈4-30pJ/write).We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset. |
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