A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks
Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these app...
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sg-ntu-dr.10356-809072020-03-07T13:24:44Z A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks Narasimman, Govind Roy, Subhrajit Fong, Xuanyao Roy, Kaushik Chang, Chip-Hong Basu, Arindam School of Electrical and Electronic Engineering 2016 IEEE International Symposium on Circuits and Systems (ISCAS) STDP-Synapse Domain wall Magnet-Synapse Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these approaches require high voltages (≈3-12V) for weight update and entail high energy for learning (≈4-30pJ/write).We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset. Accepted version 2016-08-22T07:01:28Z 2019-12-06T14:17:09Z 2016-08-22T07:01:28Z 2019-12-06T14:17:09Z 2016 2016 Conference Paper Narasimman, G., Roy, S., Fong, X., Roy, K., Chang, C.-H., & Basu, A. (2016). A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 914-917. https://hdl.handle.net/10356/80907 http://hdl.handle.net/10220/41169 10.1109/ISCAS.2016.7527390 194148 en © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2016.7527390]. 4 p. application/pdf |
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STDP-Synapse Domain wall Magnet-Synapse |
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STDP-Synapse Domain wall Magnet-Synapse Narasimman, Govind Roy, Subhrajit Fong, Xuanyao Roy, Kaushik Chang, Chip-Hong Basu, Arindam A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| description |
Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these approaches require high voltages (≈3-12V) for weight update and entail high energy for learning (≈4-30pJ/write).We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Narasimman, Govind Roy, Subhrajit Fong, Xuanyao Roy, Kaushik Chang, Chip-Hong Basu, Arindam |
| format |
Conference or Workshop Item |
| author |
Narasimman, Govind Roy, Subhrajit Fong, Xuanyao Roy, Kaushik Chang, Chip-Hong Basu, Arindam |
| author_sort |
Narasimman, Govind |
| title |
A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| title_short |
A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| title_full |
A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| title_fullStr |
A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| title_full_unstemmed |
A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks |
| title_sort |
low-voltage, low power stdp synapse implementation using domain-wall magnets for spiking neural networks |
| publishDate |
2016 |
| url |
https://hdl.handle.net/10356/80907 http://hdl.handle.net/10220/41169 |
| _version_ |
1681041263442264064 |