Analysis and optimization of a deeply pipelined FPGA soft processor

• Main Authors: Cheah, Hui Yan, Fahmy, Suhaib A., Kapre, Nachiket
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 主題: Computer Science and Engineering
• 在線閱讀: https://hdl.handle.net/10356/81037; http://hdl.handle.net/10220/39115
• 機構: Nanyang Technological University

FPGA soft processors have been shown to achieve high frequency when designed around the specific capabilities of heterogenous resources on modern FPGAs. However, such performance comes at a cost of deep pipelines, which can result in a larger number of idle cycles when executing programs with long d...