Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs
Fine-grained dataflow processing of sparse matrix-solve computation (Ax = b) in the SPICE circuit simulator can provide an order of magnitude performance improvement on modern FPGAs. Matrix solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly durin...
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sg-ntu-dr.10356-811912020-05-28T07:18:28Z Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs Kapre, Nachiket DeHon, Andre School of Computer Engineering 2009 International Conference on Field-Programmable Technology (FPT) Computer Science and Engineering Fine-grained dataflow processing of sparse matrix-solve computation (Ax = b) in the SPICE circuit simulator can provide an order of magnitude performance improvement on modern FPGAs. Matrix solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly during the simulation, once for every iteration. We process sparse-matrix computation generated from the SPICE-oriented KLU solver in dataflow fashion across multiple spatial floating-point operators coupled to high-bandwidth on-chip memories and interconnected by a low-latency network. Using this approach, we are able to show speedups of 1.2-64x (geometric mean of 8.8x ) for a range of circuits and benchmark matrices when comparing double-precision implementations on a 250 MHz Xilinx Virtex-5 FPGA (65 nm) and an Intel Core i7 965 processor (45 nm). Accepted version 2015-12-21T07:43:39Z 2019-12-06T14:23:19Z 2015-12-21T07:43:39Z 2019-12-06T14:23:19Z 2009 Conference Paper Kapre, N., & DeHon, A. (2009). Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs. 2009 International Conference on Field-Programmable Technology, 190-198. https://hdl.handle.net/10356/81191 http://hdl.handle.net/10220/39196 10.1109/FPT.2009.5377665 en © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPT.2009.5377665]. 9 p. application/pdf |
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Computer Science and Engineering Kapre, Nachiket DeHon, Andre Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
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Fine-grained dataflow processing of sparse matrix-solve computation (Ax = b) in the SPICE circuit simulator can provide an order of magnitude performance improvement on modern FPGAs. Matrix solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly during the simulation, once for every iteration. We process sparse-matrix computation generated from the SPICE-oriented KLU solver in dataflow fashion across multiple spatial floating-point operators coupled to high-bandwidth on-chip memories and interconnected by a low-latency network. Using this approach, we are able to show speedups of 1.2-64x (geometric mean of 8.8x ) for a range of circuits and benchmark matrices when comparing double-precision implementations on a 250 MHz Xilinx Virtex-5 FPGA (65 nm) and an Intel Core i7 965 processor (45 nm). |
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School of Computer Engineering |
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School of Computer Engineering Kapre, Nachiket DeHon, Andre |
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Conference or Workshop Item |
author |
Kapre, Nachiket DeHon, Andre |
author_sort |
Kapre, Nachiket |
title |
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
title_short |
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
title_full |
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
title_fullStr |
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
title_full_unstemmed |
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs |
title_sort |
parallelizing sparse matrix solve for spice circuit simulation using fpgas |
publishDate |
2015 |
url |
https://hdl.handle.net/10356/81191 http://hdl.handle.net/10220/39196 |
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1681059594658381824 |