Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

• Main Authors: Wang, Bo, Nguyen, Truc Quynh, Do, Anh Tuan, Zhou, Jun, Je, Minkyu, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2016
• Subjects: Energy efficiency improvement; Ultra-low voltage SRAM design; Bitline leakage equalization; Content addressable memory
• Online Access: https://hdl.handle.net/10356/81737; http://hdl.handle.net/10220/39677
• Institution: Nanyang Technological University

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to...