Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

• Main Authors: Wang, Bo, Nguyen, Truc Quynh, Do, Anh Tuan, Zhou, Jun, Je, Minkyu, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2016
• Subjects: Energy efficiency improvement; Ultra-low voltage SRAM design; Bitline leakage equalization; Content addressable memory
• Online Access: https://hdl.handle.net/10356/81737; http://hdl.handle.net/10220/39677
• Institution: Nanyang Technological University

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 μs. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V ~ 0.6 V by the proposed CAM-assisted circuit.