A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline

• Main Authors: Zhou, Rong, Chong, Kwen-Siong, Lin, Tong, Gwee, Bah Hwee, Chang, Joseph Sylvester
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2016
• Subjects: Critical path; Dual-rail; Dynamic voltage scaling; Fast transition; Fine-grained; Asynchronous; Timing-tolerant
• Online Access: https://hdl.handle.net/10356/82870; http://hdl.handle.net/10220/40367
• Institution: Nanyang Technological University

We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports...