A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline

We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports...

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Main Authors: Zhou, Rong, Chong, Kwen-Siong, Lin, Tong, Gwee, Bah Hwee, Chang, Joseph Sylvester
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2016
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Online Access:https://hdl.handle.net/10356/82870
http://hdl.handle.net/10220/40367
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-828702020-09-26T22:14:58Z A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline Zhou, Rong Chong, Kwen-Siong Lin, Tong Gwee, Bah Hwee Chang, Joseph Sylvester School of Electrical and Electronic Engineering 2015 IEEE International Symposium on Circuits and Systems (ISCAS) Temasek Laboratories Critical path Dual-rail Dynamic voltage scaling Fast transition Fine-grained Asynchronous Timing-tolerant We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports fasttransition DVS within one-and-a-half clock duration per operation, and its operation remains error-free during that duration; we define such attribute as half-clock-tolerant. Third, it consists of a single power source (single-VDD) which supports three voltage scales (1.2V, 0.8V and 0.5V) for power/speed tradeoffs, and has standardized 1.2V output to seamlessly interface with other proposed/conventional pipelines. These attributes are achieved due to the embodiment of a DVS power unit, asynchronous building blocks to control/synchronize the operation, a dual-rail critical path to innately detect the completion of the operation, and level shifters to standardize the output voltage. We demonstrate our proposed pipeline by designing a multiplier embodied in a Fast Fourier Transform processor (@65nm CMOS). We show that the multiplier based on our proposed pipeline, on average, is 1.94× more power-efficient than that based on a conventional pipeline ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version 2016-04-01T03:10:54Z 2019-12-06T15:07:18Z 2016-04-01T03:10:54Z 2019-12-06T15:07:18Z 2015 Conference Paper Zhou, R., Chong, K.-S., Lin, T., Gwee, B. H., & Chang, J. S. (2015). A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2589-2592. https://hdl.handle.net/10356/82870 http://hdl.handle.net/10220/40367 10.1109/ISCAS.2015.7169215 en © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2015.7169215]. 4 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Critical path
Dual-rail
Dynamic voltage scaling
Fast transition
Fine-grained
Asynchronous
Timing-tolerant
spellingShingle Critical path
Dual-rail
Dynamic voltage scaling
Fast transition
Fine-grained
Asynchronous
Timing-tolerant
Zhou, Rong
Chong, Kwen-Siong
Lin, Tong
Gwee, Bah Hwee
Chang, Joseph Sylvester
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
description We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports fasttransition DVS within one-and-a-half clock duration per operation, and its operation remains error-free during that duration; we define such attribute as half-clock-tolerant. Third, it consists of a single power source (single-VDD) which supports three voltage scales (1.2V, 0.8V and 0.5V) for power/speed tradeoffs, and has standardized 1.2V output to seamlessly interface with other proposed/conventional pipelines. These attributes are achieved due to the embodiment of a DVS power unit, asynchronous building blocks to control/synchronize the operation, a dual-rail critical path to innately detect the completion of the operation, and level shifters to standardize the output voltage. We demonstrate our proposed pipeline by designing a multiplier embodied in a Fast Fourier Transform processor (@65nm CMOS). We show that the multiplier based on our proposed pipeline, on average, is 1.94× more power-efficient than that based on a conventional pipeline
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Zhou, Rong
Chong, Kwen-Siong
Lin, Tong
Gwee, Bah Hwee
Chang, Joseph Sylvester
format Conference or Workshop Item
author Zhou, Rong
Chong, Kwen-Siong
Lin, Tong
Gwee, Bah Hwee
Chang, Joseph Sylvester
author_sort Zhou, Rong
title A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
title_short A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
title_full A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
title_fullStr A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
title_full_unstemmed A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
title_sort single-vdd half-clock-tolerant fine-grained dynamic voltage scaling pipeline
publishDate 2016
url https://hdl.handle.net/10356/82870
http://hdl.handle.net/10220/40367
_version_ 1681056048234889216