Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster

• Main Authors: Moorthy, Pradeep, Kapre, Nachiket
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: Computer Science and Engineering
• Online Access: https://hdl.handle.net/10356/83649; http://hdl.handle.net/10220/39205
• Institution: Nanyang Technological University

Commodity SoCs with hybrid architectures that combine CPUs with programmable FPGA fabric such as the Xilinx Zynq SoC have become a competitive energy-efficient platform for addressing irregular parallelism in graph problems. In this paper, we prototype a 32-node cluster composed from these Zynq SoC...