A 1.2V 80MS/S sample and hold for ADC applications

A 1.2V 80MS/S sample and hold for ADC applications

This Paper presents the design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch. A rai...

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Main Authors: Reddy, Y. Sunil Gavaskar., Liter, Siek.
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/84655
http://hdl.handle.net/10220/12138
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-846552020-03-07T13:24:45Z A 1.2V 80MS/S sample and hold for ADC applications Reddy, Y. Sunil Gavaskar. Liter, Siek. School of Electrical and Electronic Engineering International Conference on Devices, Circuits and Systems (2012 : Coimbatore, India) DRNTU::Engineering::Electrical and electronic engineering This Paper presents the design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch. A rail-to-rail ICMR op-amp, is used to extend the input operating range. The designed sample and hold operates at 80MS/s from 1.2V supply. The circuits are designed using CSM 0.18um technology in cadence environment and power consumption estimated was 4.15mW. 2013-07-25T01:34:33Z 2019-12-06T15:48:58Z 2013-07-25T01:34:33Z 2019-12-06T15:48:58Z 2012 2012 Conference Paper Reddy, Y. S. G., & Liter, S. (2012). A 1.2V 80MS/S sample and hold for ADC applications. 2012 International Conference on Devices, Circuits and Systems (ICDCS). https://hdl.handle.net/10356/84655 http://hdl.handle.net/10220/12138 10.1109/ICDCSyst.2012.6188668 en © 2012 IEEE.
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Reddy, Y. Sunil Gavaskar.
Liter, Siek.
A 1.2V 80MS/S sample and hold for ADC applications
description This Paper presents the design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch. A rail-to-rail ICMR op-amp, is used to extend the input operating range. The designed sample and hold operates at 80MS/s from 1.2V supply. The circuits are designed using CSM 0.18um technology in cadence environment and power consumption estimated was 4.15mW.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Reddy, Y. Sunil Gavaskar.
Liter, Siek.
format Conference or Workshop Item
author Reddy, Y. Sunil Gavaskar.
Liter, Siek.
author_sort Reddy, Y. Sunil Gavaskar.
title A 1.2V 80MS/S sample and hold for ADC applications
title_short A 1.2V 80MS/S sample and hold for ADC applications
title_full A 1.2V 80MS/S sample and hold for ADC applications
title_fullStr A 1.2V 80MS/S sample and hold for ADC applications
title_full_unstemmed A 1.2V 80MS/S sample and hold for ADC applications
title_sort 1.2v 80ms/s sample and hold for adc applications
publishDate 2013
url https://hdl.handle.net/10356/84655
http://hdl.handle.net/10220/12138
_version_ 1681041868184354816

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