A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique

• Main Authors: Liang, Zhipeng, Yi, Xiang, Yang, Kaituo, Boon, Chirn Chye
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Calibration Free; CMOS Phase-Locked Loop; DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/85905; http://hdl.handle.net/10220/48325
• Institution: Nanyang Technological University

Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful calibrations with extra silicon area and adjusting time (20 ms measured) to achieve low phase noise. For scenarios requiring short settling time such as frequency modulation, such a time consuming calibration is undesirable. This letter presents a phase-switching technique for fractional-N mode SSPLL to eliminate this calibration. The principle of the technique is analyzed and a prototype is fabricated in 65-nm CMOS technology. Even without calibration, the frequency synthesizer achieves a figure of merit of -234.3 dB under fractional-N operation, with 13.3-mW power consumption at 1.2-V supply.