A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique

• Main Authors: Liang, Zhipeng, Yi, Xiang, Yang, Kaituo, Boon, Chirn Chye
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2019
• 主題: Calibration Free; CMOS Phase-Locked Loop; DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/85905; http://hdl.handle.net/10220/48325
• 機構: Nanyang Technological University

Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful...