An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations

• المؤلف الرئيسي: Zhang, Yufei
• مؤلفون آخرون: Chang Chip Hong
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/89387; http://hdl.handle.net/10220/47113
• المؤسسة: Nanyang Technological University

Shrinking of the device feature size allows high complexity systems to be designed and integrated with into a single chip but also causes potential issues on system reliability. Existing coding techniques can only detect and correct transmission and storage errors but not errors occurred in arithmet...