An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator

• Main Authors: Chan, Pak Kwong, Susanti, Yulia, Ong, Vincent K. S.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/90557; http://hdl.handle.net/10220/6377
• Institution: Nanyang Technological University

This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution Successive Approximation Analogto- Digital Converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18μm CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2μW at a single supply of 1.8V whilst sampling at a frequency of 64kHz, with conversion time of 187.5μs. The energy per quantization level is less than 0.1pJ/level.