An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator

This paper presents a new offset-biased autozero comparator for the design of an ultra low-power...

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Main Authors:	Chan, Pak Kwong, Susanti, Yulia, Ong, Vincent K. S.
Other Authors:	School of Electrical and Electronic Engineering
Format:	Conference or Workshop Item
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	https://hdl.handle.net/10356/90557 http://hdl.handle.net/10220/6377
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-905572020-03-07T13:24:46Z An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator Chan, Pak Kwong Susanti, Yulia Ong, Vincent K. S. School of Electrical and Electronic Engineering IEEE Asia Pacific Conference on Circuits and Systems (2008 : Macau) DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution Successive Approximation Analogto- Digital Converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18μm CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2μW at a single supply of 1.8V whilst sampling at a frequency of 64kHz, with conversion time of 187.5μs. The energy per quantization level is less than 0.1pJ/level. Published version 2010-08-31T03:23:17Z 2019-12-06T17:49:48Z 2010-08-31T03:23:17Z 2019-12-06T17:49:48Z 2008 2008 Conference Paper Chan, P. K., Susanti, Y., & Ong, V. K. S. (2009). An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator. In proceedings of the 9th IEEE Asia Pacific Conference on Circuits and Systems: Macau, (pp.284-287). https://hdl.handle.net/10356/90557 http://hdl.handle.net/10220/6377 10.1109/APCCAS.2008.4746015 en © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Chan, Pak Kwong Susanti, Yulia Ong, Vincent K. S. An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
description	This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution Successive Approximation Analogto- Digital Converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18μm CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2μW at a single supply of 1.8V whilst sampling at a frequency of 64kHz, with conversion time of 187.5μs. The energy per quantization level is less than 0.1pJ/level.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Chan, Pak Kwong Susanti, Yulia Ong, Vincent K. S.
format	Conference or Workshop Item
author	Chan, Pak Kwong Susanti, Yulia Ong, Vincent K. S.
author_sort	Chan, Pak Kwong
title	An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
title_short	An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
title_full	An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
title_fullStr	An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
title_full_unstemmed	An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
title_sort	ultra low-power successive approximation adc using an offset-biased auto-zero comparator
publishDate	2010
url	https://hdl.handle.net/10356/90557 http://hdl.handle.net/10220/6377
_version_	1681037473695662080

An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator

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