Body-bootstrapped-buffer circuit for CMOS static power reduction

• Main Authors: Loy, Liang Yu, Zhang, Weijia, Kong, Zhi Hui, Goh, Wang Ling, Yeo, Kiat Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/90765; http://hdl.handle.net/10220/6378
• Institution: Nanyang Technological University

In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limited’s (CHRT) 0.25-μm, 0.18-μm and Berkeley Predictive Technology Model’s (BPTM) 90-nm processes showed good trade-offs between power savings and delay.