FPGA implementation of digital filters synthesized using the frequency-response masking technique
The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the rando...
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| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2009
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| Online Access: | https://hdl.handle.net/10356/90768 http://hdl.handle.net/10220/4589 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this
paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM. |
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