FPGA implementation of digital filters synthesized using the frequency-response masking technique

The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the rando...

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Main Authors:	Zheng, H. Q., Lim, Yong Ching, Yu, Ya Jun, Foo, Say Wei
Other Authors:	IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia)
Format:	Conference or Workshop Item
Language:	English
Published:	2009
Online Access:	https://hdl.handle.net/10356/90768 http://hdl.handle.net/10220/4589
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-90768
record_format	dspace
spelling	sg-ntu-dr.10356-907682019-12-06T17:53:38Z FPGA implementation of digital filters synthesized using the frequency-response masking technique Zheng, H. Q. Lim, Yong Ching Yu, Ya Jun Foo, Say Wei IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia) The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM. Accepted version 2009-04-28T04:44:24Z 2019-12-06T17:53:38Z 2009-04-28T04:44:24Z 2019-12-06T17:53:38Z 2001 2001 Conference Paper Lim, Y. C., Yu, Y. J., Zheng, H.Q., & Foo, S.W. (2001). FPGA implementation of digital filters synthesized using the frequency-response masking technique. IEEE International Symposium on Circuits and Systems 2001: (pp. 173-176). Singapore: National University of Singapore. https://hdl.handle.net/10356/90768 http://hdl.handle.net/10220/4589 en © 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
description	The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM.
author2	IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia)
author_facet	IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia) Zheng, H. Q. Lim, Yong Ching Yu, Ya Jun Foo, Say Wei
format	Conference or Workshop Item
author	Zheng, H. Q. Lim, Yong Ching Yu, Ya Jun Foo, Say Wei
spellingShingle	Zheng, H. Q. Lim, Yong Ching Yu, Ya Jun Foo, Say Wei FPGA implementation of digital filters synthesized using the frequency-response masking technique
author_sort	Zheng, H. Q.
title	FPGA implementation of digital filters synthesized using the frequency-response masking technique
title_short	FPGA implementation of digital filters synthesized using the frequency-response masking technique
title_full	FPGA implementation of digital filters synthesized using the frequency-response masking technique
title_fullStr	FPGA implementation of digital filters synthesized using the frequency-response masking technique
title_full_unstemmed	FPGA implementation of digital filters synthesized using the frequency-response masking technique
title_sort	fpga implementation of digital filters synthesized using the frequency-response masking technique
publishDate	2009
url	https://hdl.handle.net/10356/90768 http://hdl.handle.net/10220/4589
_version_	1681035750484738048

FPGA implementation of digital filters synthesized using the frequency-response masking technique

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