A review of 0.18-µm full adder performances for tree structured arithmetic circuits

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation ci...

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Bibliographic Details
Main Authors: Chang, Chip Hong, Gu, Jiang Min, Zhang, Mingyan
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2009
Subjects:
Online Access:https://hdl.handle.net/10356/91436
http://hdl.handle.net/10220/6013
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Institution: Nanyang Technological University
Language: English