Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

The effective channel length L-eff and total external series resistance R-TOTEXT of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L-eff...

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Main Authors: Seah, Lionel Siau Hing, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2009
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/91517
http://hdl.handle.net/10220/4708
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-915172020-03-07T14:02:40Z Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment Seah, Lionel Siau Hing Yeo, Kiat Seng Ma, Jianguo Do, Manh Anh School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The effective channel length L-eff and total external series resistance R-TOTEXT of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L-eff and R-TOTEXT extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage V(sb) ≥ 0 V conditions. Published version 2009-07-28T03:38:09Z 2019-12-06T18:07:06Z 2009-07-28T03:38:09Z 2019-12-06T18:07:06Z 2001 2001 Journal Article Seah, S. H., Yeo, K. S., Ma, J. G., & Do, M. A. (2001). Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment. IEEE Transactions on Electron Devices, 48(5), 1001-1004. 0018-9383 https://hdl.handle.net/10356/91517 http://hdl.handle.net/10220/4708 10.1109/16.918250 en IEEE transactions on electron devices © 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Seah, Lionel Siau Hing
Yeo, Kiat Seng
Ma, Jianguo
Do, Manh Anh
Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
description The effective channel length L-eff and total external series resistance R-TOTEXT of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L-eff and R-TOTEXT extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage V(sb) ≥ 0 V conditions.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Seah, Lionel Siau Hing
Yeo, Kiat Seng
Ma, Jianguo
Do, Manh Anh
format Article
author Seah, Lionel Siau Hing
Yeo, Kiat Seng
Ma, Jianguo
Do, Manh Anh
author_sort Seah, Lionel Siau Hing
title Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
title_short Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
title_full Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
title_fullStr Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
title_full_unstemmed Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
title_sort effective channel length and external series resistance models of scaled ldd pmosfets operating in a bi-mos hybrid-mode environment
publishDate 2009
url https://hdl.handle.net/10356/91517
http://hdl.handle.net/10220/4708
_version_ 1681042536308670464

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