A study of on-chip stacked multi-loop spiral inductors

• Main Authors: Zhang, Yue Ping, Yang, Kai, Yin, Wen Yan, Shi, Jinglin, Kang, Kai, Mao, Jun Fa
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92314; http://hdl.handle.net/10220/6264
• Institution: Nanyang Technological University

This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.