A study of on-chip stacked multi-loop spiral inductors
This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, a...
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sg-ntu-dr.10356-923142020-03-07T14:02:39Z A study of on-chip stacked multi-loop spiral inductors Zhang, Yue Ping Yang, Kai Yin, Wen Yan Shi, Jinglin Kang, Kai Mao, Jun Fa School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs. Published version 2010-05-05T06:50:42Z 2019-12-06T18:21:12Z 2010-05-05T06:50:42Z 2019-12-06T18:21:12Z 2008 2008 Journal Article Yang, K., Yin, W. Y., Shi, J., Kang, K., Mao, J. F., & Zhang, Y. P. (2008). Study of On-Chip Stacked Multiloop Spiral Inductors. IEEE Transactions on Electron Devices. 55(11), 3236-3245. 0018-9383 https://hdl.handle.net/10356/92314 http://hdl.handle.net/10220/6264 10.1109/TED.2008.2004648 en IEEE transactions on electron devices © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 10 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Zhang, Yue Ping Yang, Kai Yin, Wen Yan Shi, Jinglin Kang, Kai Mao, Jun Fa A study of on-chip stacked multi-loop spiral inductors |
| description |
This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of
stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency
integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement
equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a
larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing
new silicon-based passive devices used in RFICs. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Zhang, Yue Ping Yang, Kai Yin, Wen Yan Shi, Jinglin Kang, Kai Mao, Jun Fa |
| format |
Article |
| author |
Zhang, Yue Ping Yang, Kai Yin, Wen Yan Shi, Jinglin Kang, Kai Mao, Jun Fa |
| author_sort |
Zhang, Yue Ping |
| title |
A study of on-chip stacked multi-loop spiral inductors |
| title_short |
A study of on-chip stacked multi-loop spiral inductors |
| title_full |
A study of on-chip stacked multi-loop spiral inductors |
| title_fullStr |
A study of on-chip stacked multi-loop spiral inductors |
| title_full_unstemmed |
A study of on-chip stacked multi-loop spiral inductors |
| title_sort |
study of on-chip stacked multi-loop spiral inductors |
| publishDate |
2010 |
| url |
https://hdl.handle.net/10356/92314 http://hdl.handle.net/10220/6264 |
| _version_ |
1681034641905025024 |