An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes th...

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Main Authors: Jiang, Shan, Do, Manh Anh, Yeo, Kiat Seng, Lim, Wei Meng
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2010
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Online Access:https://hdl.handle.net/10356/92397
http://hdl.handle.net/10220/6256
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-923972020-03-07T14:02:41Z An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit Jiang, Shan Do, Manh Anh Yeo, Kiat Seng Lim, Wei Meng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-µm CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively. Published version 2010-05-05T03:33:29Z 2019-12-06T18:22:35Z 2010-05-05T03:33:29Z 2019-12-06T18:22:35Z 2008 2008 Journal Article Jiang, S., Do, M. A., Yeo, K. S., & Lim, W. M. (2008). An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE Transactions on Circuits and Systems—I. 55(6), 1430-1440. 1549-8328 https://hdl.handle.net/10356/92397 http://hdl.handle.net/10220/6256 10.1109/TCSI.2008.916613 en IEEE transactions on circuits and systems—I © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 11 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Jiang, Shan
Do, Manh Anh
Yeo, Kiat Seng
Lim, Wei Meng
An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
description This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-µm CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Jiang, Shan
Do, Manh Anh
Yeo, Kiat Seng
Lim, Wei Meng
format Article
author Jiang, Shan
Do, Manh Anh
Yeo, Kiat Seng
Lim, Wei Meng
author_sort Jiang, Shan
title An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
title_short An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
title_full An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
title_fullStr An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
title_full_unstemmed An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
title_sort 8-bit 200-msample/s pipelined adc with mixed-mode front-end s/h circuit
publishDate 2010
url https://hdl.handle.net/10356/92397
http://hdl.handle.net/10220/6256
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