An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit

• Main Authors: Jiang, Shan, Do, Manh Anh, Yeo, Kiat Seng, Lim, Wei Meng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92397; http://hdl.handle.net/10220/6256
• Institution: Nanyang Technological University

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes th...