A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications

• Main Authors: Sunny, Sharma, Chen, Yong, Boon, Chirn Chye
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: 1.5-bit/cycle; ADC; Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92451; http://hdl.handle.net/10220/49924
• Institution: Nanyang Technological University

This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.