A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications

This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erro...

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Bibliographic Details
Main Authors: Sunny, Sharma, Chen, Yong, Boon, Chirn Chye
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2019
Subjects:
ADC
Online Access:https://hdl.handle.net/10356/92451
http://hdl.handle.net/10220/49924
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Institution: Nanyang Technological University
Language: English

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