A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration

• Main Authors: Yin, J. K., Chan, Pak Kwong
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/92971; http://hdl.handle.net/10220/6253
• 機構: Nanyang Technological University

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process....