Fully symmetrical monolithic transformer (true 1:1) for silicon RFIC

• Main Authors: Lim, Chee Chong, Yeo, Kiat Seng, Chew, Kok Wai Johnny, Cabuk, Alper, Gu, Jiang Min, Lim, Suh Fei, Boon, Chirn Chye, Do, Manh Anh
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92986; http://hdl.handle.net/10220/6261
• Institution: Nanyang Technological University

A novel on-chip transformer configuration that gives an identical inductor pair, a higher individual coil self-resonant frequency (SRF), and excellent area efficiency are presented. This technique involves the unique way of inter-crossing the transformer’s primary and secondary coils using multiple metallization layers. Truly symmetrical transformer configuration (100%) is demonstrated using minimum die size. Thus, a true 1 : 1 transformer has been realized on silicon. The effects of the parasitic within the transformer are represented by an equivalent-circuit model. Accurate semiempirical expressions describing the circuit components are provided based on the various layout parameters. Of all the transformer structures presented, the two designs occupying the minimum silicon area by a factor of > 2x have been selected for performance evaluation of the SRF, coupling coefficient, input impedance, quality factor, and inductance. The transmission line transformer mode has also been studied to examine the designs’ performance in the differential mode. The second proposed design reported in this paper, with enhancements in S21 and k performance, is created by adding a unique routing technique onto the first proposed structure. The method presented is fully compatible with the standard foundry CMOS processes. The silicon data reported in this study are based on Chartered Semiconductor Manufacturing’s 0.13-µm RF CMOS technology node.