Complex shaped on-wafer interconnects modeling for CMOS RFICs
A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empir...
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| Main Authors: | , , , , |
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| 其他作者: | |
| 格式: | Article |
| 語言: | English |
| 出版: |
2010
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/93083 http://hdl.handle.net/10220/6252 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | A model development methodology for complex shaped
on-wafer interconnects is presented. The equivalent circuit of the entire
interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the
proposed model can be easily incorporated with commercial electronic
design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz. |
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