High-throughput memory-based architecture for DHT using a new convolutional formulation

A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization o...

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Main Authors:	Swamy, M. N. S., Meher, Pramod Kumar, Patra, Jagdish Chandra
Other Authors:	School of Computer Engineering
Format:	Article
Language:	English
Published:	2011
Subjects:	DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
Online Access:	https://hdl.handle.net/10356/94342 http://hdl.handle.net/10220/7103
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-94342
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spelling	sg-ntu-dr.10356-943422020-05-28T07:17:52Z High-throughput memory-based architecture for DHT using a new convolutional formulation Swamy, M. N. S. Meher, Pramod Kumar Patra, Jagdish Chandra School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures. Accepted version 2011-09-22T03:31:18Z 2019-12-06T18:54:32Z 2011-09-22T03:31:18Z 2019-12-06T18:54:32Z 2007 2007 Journal Article Meher, P. K., Patra, J. C., & Swamy, M. N. S. (2007). High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(7), 606-610. 1549-7747 https://hdl.handle.net/10356/94342 http://hdl.handle.net/10220/7103 10.1109/TCSII.2007.894407 119086 en IEEE transactions on circuits and Systems II: express briefs © 2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSII.2007.894407]. 5 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
spellingShingle	DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures Swamy, M. N. S. Meher, Pramod Kumar Patra, Jagdish Chandra High-throughput memory-based architecture for DHT using a new convolutional formulation
description	A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures.
author2	School of Computer Engineering
author_facet	School of Computer Engineering Swamy, M. N. S. Meher, Pramod Kumar Patra, Jagdish Chandra
format	Article
author	Swamy, M. N. S. Meher, Pramod Kumar Patra, Jagdish Chandra
author_sort	Swamy, M. N. S.
title	High-throughput memory-based architecture for DHT using a new convolutional formulation
title_short	High-throughput memory-based architecture for DHT using a new convolutional formulation
title_full	High-throughput memory-based architecture for DHT using a new convolutional formulation
title_fullStr	High-throughput memory-based architecture for DHT using a new convolutional formulation
title_full_unstemmed	High-throughput memory-based architecture for DHT using a new convolutional formulation
title_sort	high-throughput memory-based architecture for dht using a new convolutional formulation
publishDate	2011
url	https://hdl.handle.net/10356/94342 http://hdl.handle.net/10220/7103
_version_	1681057920468385792

High-throughput memory-based architecture for DHT using a new convolutional formulation

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