A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter

• Main Authors: Cai, Deyun, Fu, Haipeng, Ren, Junyan, Li, Wei, Li, Ning, Yu, Hao, Yeo, Kiat Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/94748; http://hdl.handle.net/10220/8561
• Institution: Nanyang Technological University

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-$mu$m CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm$,times,$ 0.86 mm. The reference spur of the proposed PLL is measured to be ${-}80$ dBc/${-}74$ dBc and an in-band phase noise of ${-}103$ dBc/Hz at 100 kHz offset is achieved.