A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications

• Main Authors: Do, Anh Tuan, Lam, Chun Kit, Tan, Yung Sern, Yeo, Kiat Seng, Cheong, Jia Hao, Zou, Xiaodan, Yao, Lei, Cheng, Kuang Wei, Je, Minkyu
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/95719; http://hdl.handle.net/10220/11771
• Institution: Nanyang Technological University

This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.