A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to...

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Main Authors: Low, Jeremy Yung Shern, Chang, Chip Hong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
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Online Access:https://hdl.handle.net/10356/95909
http://hdl.handle.net/10220/11327
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-959092020-03-07T14:02:45Z A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS Low, Jeremy Yung Shern Chang, Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in {2n - 1,2n,2n + 1} RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for n = 5 , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 μm standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average. 2013-07-12T06:19:12Z 2019-12-06T19:23:15Z 2013-07-12T06:19:12Z 2019-12-06T19:23:15Z 2012 2012 Journal Article Low, J. Y. S., & Chang, C. H. (2012). A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS. IEEE Transactions on Circuits and Systems I : Regular Papers, 59(12), 2911-2919. 1549-8328 https://hdl.handle.net/10356/95909 http://hdl.handle.net/10220/11327 10.1109/TCSI.2012.2206491 en IEEE transactions on circuits and systems I : regular papers © 2012 IEEE.
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Low, Jeremy Yung Shern
Chang, Chip Hong
A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
description Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in {2n - 1,2n,2n + 1} RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for n = 5 , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 μm standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Low, Jeremy Yung Shern
Chang, Chip Hong
format Article
author Low, Jeremy Yung Shern
Chang, Chip Hong
author_sort Low, Jeremy Yung Shern
title A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
title_short A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
title_full A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
title_fullStr A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
title_full_unstemmed A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
title_sort vlsi efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 rns
publishDate 2013
url https://hdl.handle.net/10356/95909
http://hdl.handle.net/10220/11327
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